RISC-V Assembly and Shellcode Series

Learn about RISC-V from the ground up with me. The intent of this series is to write some generic payloads, some shellcode, and mostly learn about a new ISA.

This series is specifically on the topic of RISC-V RV64G Linux as well as some examples with RV64GC.

posts

Part 1: Introduction - Introduction to the ISA, OS dependent code, and a very basic contrived example.
Part 2: Some Complexity - Endianness, stack, pseudoinstructions, debugging, and why we cant easily load a 32-bit value immediately. Coming soon

source code

The following repositories contain the code from this project:

Build artifacts from a RISC-V system are also provided here:

riscv-1554585818.tar.gz